#if !defined ( __AVALANCHE_PCI_H_ )
#define __AVALANCHE_PCI_H_

#include "asm/mach-avalanche/generic/pal.h"

#define AV_PCI_HWIRQ			AVALANCHE_PCI /* this will come in from yamuna.h */
#define AV_PCI_HW_BASE			AV_PCI_HWIRQ
#define AV_PCI_HW_END			AV_PCI_HWIRQ
#define AV_Y_INTA_BIT			16

#define AV_PCI_SPEED                    33                      /* in Mhz */
#define AV_PCI_MAX_GRANT                255                     /* number of PCI clocks each master can take */


/*----------------------------------------
* the defines for the PCI configuration space
*
* mostly just defining the values should be enough for a new board as the basic PCIIF is
* pretty similar. but cross validate the programming when adding new board
*
*/
#define AV_PCI_BASE 			AVALANCHE_PCI_CFG_BASE
#define AV_PCI_MASTER_CONTROL		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x310 ) )
#define AV_PCI_ARBITER_CONTROL		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x184 ) )
#define AV_PCI_COMMAND			(*(volatile unsigned long *) ( AV_PCI_BASE + 0x308 ) )
#define AV_PCI_ADDRESS			(*(volatile unsigned long *) ( AV_PCI_BASE + 0x304 ) )
#define AV_PCI_DATA			(*(volatile unsigned long *) ( AV_PCI_BASE + 0x300 ) )
#define AV_PCI_INTR_CLEAR		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x14 ) )
#define AV_PCI_INTR_STATE		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x10 ) )
#define AV_PCI_INTR_ENABLE		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x20 ) )
#define AV_PCI_INTR_DISABLE		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x24 ) )
#define AV_PCI_BE_INTR_ENABLE		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x30 ) )
#define AV_PCI_BE_INTR_DISABLE		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x34 ) )
#define AV_PCI_SLAVE_CACHE		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x10C ) )
#define AV_PCI_SLAVE_MASK_0		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x110 ) )
#define AV_PCI_SLAVE_TRANS_0		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x1c0 ) )
#define AV_PCI_CFG_DONE_REG		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x180 ) )
#define AV_PCI_SLAVE_CONTROL		AV_PCI_CFG_DONE_REG
#define AV_PCI_READ_CFG			0x1
#define AV_PCI_WRITE_CFG		0x0
#define AV_PCI_READ_IO			0x5
#define AV_PCI_WRITE_IO			0x4
#define AV_PCI_RUN_COMMAND		0x2
#define AV_PCI_BUSY_MASK		0x80000000
#define AV_PCI_BUSY			0
#define AV_PCIIF_MASTER_DEVICE		0x10000
#define AV_PCI_ALL_BYTES		0xf0
#define AV_PCI_CFG_DONE			0x1		
#define AV_PCI_ENABLE_BUSMASTER		0x700			/* enable cfg, io, mem of io master even if slave not enabled */
#define AV_PCI_ARBITER_ON		0x8000000f		/* turn on arbiter, clear all masters as sane to start */
#define AV_PCI_VBUS_SPACE_BEGIN 	0x40000000
#define AV_PCI_VBUS_SPACE_END		0x7fffffff
#define AV_PCI_MASTER_ABORT		0x4
#define AV_PCI_TARGET_ABORT		0x2

#define AV_PCI_SLAVE_0_ENABLE		0x00010000
#define AV_PCI_SLAVE_1_ENABLE		0x00020000
#define AV_PCI_SLAVE_2_ENABLE		0x00040000
#define AV_PCI_SLAVE_3_ENABLE		0x00080000
#define AV_PCI_SLAVE_4_ENABLE		0x00100000
#define AV_PCI_SLAVE_5_ENABLE		0x00200000

#define AV_PCI_SLAVE_MASK_VALUE		0xe0000000		/* pci_space_begin to end of address space, nonprefetchable, anywhere */
#define AV_PCI_SLAVE_0_MIRROR		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x1e0 ) )
#define AV_PCI_SLAVE_0_BASE		0x00000000
#define AV_PCI_SLAVE_CMD_STATUS		(*(volatile unsigned long *) ( AV_PCI_BASE + 0x104 ) )
#define AV_PCI_SLAVE_RUN_CMD		0xf0000006
#define AV_PCI_BUSMASTER_ENABLE     	0x4
#define AV_PCI_MEMRESPONSE_ENABLE	0x2
#define AV_PCI_IORESPONSE_ENABLE	0x1
#define AV_PCI_PREFETCH_ENABLE          (1<<3)
#define PREFETCH_SIZE_32		(1<<5)
#define AV_PCI_SLAVE_START		( AV_PCI_BUSMASTER_ENABLE | AV_PCI_MEMRESPONSE_ENABLE | AV_PCI_IORESPONSE_ENABLE )


#endif /* __AVALANCHE_PCI_H_ */
