
/*  OS Data Structure definitions  */

typedef void OS_DEVICE;
typedef void OS_SENDINFO;
typedef void OS_RECEIVEINFO;
typedef void OS_SETUP;

typedef struct hal_device  HAL_DEVICE;
typedef struct hal_private HAL_RECEIVEINFO;
typedef volatile struct hal_private HAL_RCB;

#define _CPSW_HAL
#define _CPHAL_HDMA                                                  /*+M001*/
/*#define __CPHAL_DEBUG                                                      */

#include "cpswhal.h"

typedef enum
  {
   enConnected=1, enDevFound, enInitialized, enOpened
  }DEVICE_STATE;

typedef struct
  {
  bit32 HNext;      /*< Hardware's pointer to next buffer descriptor  */
  bit32 BufPtr;     /*< Pointer to the data buffer                    */
  bit32 Off_BLen;   /*< Contains buffer offset and buffer length      */
  bit32 mode;       /*< SOP, EOP, Ownership, EOQ, Teardown, Q Starv, Length */
  void *Next;
  void *OsInfo;
  void *Eop;
#ifdef _CPHAL_HDMA
  int   (*SendComplete)(OS_SENDINFO *OsSendInfo);                    /*M001*/
#endif
#ifdef __CPHAL_DEBUG
  bit32 DbgSop;
  bit32 DbgData;
  bit32 DbgFraglist;
#endif
  }HAL_TCB;

#include "cpswhaleswitch.h"

typedef struct
          {
          HAL_TCB *TcbPool;
          HAL_TCB *TxActQueueHead;
          HAL_TCB *TxActQueueTail;
          bit32   TxActQueueCount;
          bit32   TxActive;
          int     TxServiceMax;
          HAL_TCB *LastTcbProcessed;
          char  *TcbStart;
/*          bit32 TxMisQCnt;                                                 */
/*          bit32 TxEOQCnt;                                                  */
/*          bit32 TxPacketsServiced;                                         */
/*          bit32 TxMaxServiced;                                             */
          }cppi_txcntl_s;


typedef struct
          {
          HAL_RCB *RcbPool;
          HAL_RCB *RxActQueueHead;
          HAL_RCB *RxActQueueTail;
          bit32   RxActQueueCount;
          bit32   RxActive;
          bit32u  RxServiceMax;
          char    *RcbStart;
          OS_SETUP *OsSetup;
          }cppi_rxcntl_s;

#include "cpswhalutlparams.h"

#define MAX_CHAN 8
#define MAX_QUEUE 1
#define MAX_FRAG 2
#define MAX_NEEDS 32

typedef struct hal_device
          {
          bit32u EswitchBase;
          bit32u Cpmac0Base;
          bit32u Cpmac1Base;
          bit32u HdmaBase;
          bit32u MdioBase;
          bit32u ResetBase;

          int    EswitchResetBit;
          int    Cpmac0ResetBit;
          int    Cpmac1ResetBit;
          int    MdioResetBit;
          int    Phy0ResetBit;
          int    Phy1ResetBit;
          int    HdmaResetBit;

          int    Cpmac0IntBit;
          int    Cpmac1IntBit;
          int    EswitchIntBit;

          bit32u CpuFrequency;
          bit32u EswitchFrequency;
          bit32u OneSec;
          bit32u BigEndian;

          int    EswitchDefaultCamSize;
          bit32u EswitchBufferSize;
          bit32u EswitchHostBufCount;
          int    EswitchOverFlowCount;
          int    EswitchOverFlowSize;
          void   *EswitchOverFlowArea;
          void   *EswitchCposArea;
          bit32u CurrentMode;
          bit32u CurrentPortState;
          bit32u VlanidValid[16];
          bit32u VlanidValue[16];
          bit32u VlanidInfo[16];

          bit32u TxMaxPending;
          bit32u TxServiceMax;
          bit32u RxSSBufSize;
          bit32u RxIPBufSize;
          bit32u RxServiceMax;
          bit32u RxSSNumBuffers;
          bit32u RxIPNumBuffers;

          void   *PhyState[2];
          bit32u PhyLinked[2];
          bit32u PhyNum[2];
          bit32u PhyStatus;
          bit32u EnabledPorts;

          bit32u MdioPhyMask0;
          bit32u MdioPhyMask1;

          bit32u MdioPhyMode0;
          bit32u MdioPhyMode1;
          bit32u CurrentMdioPhyMode0;
          bit32u CurrentMdioPhyMode1;

          bit32u MaxChannel;
          SUB_STRUCT SubStructs[MAX_SUB_STRUCT];

          char *DeviceInfo;
          bit32 ChIsOpen[MAX_CHAN][2];
          OS_FUNCTIONS *OsFunc;
          OS_DEVICE *OsDev;
          bit32u interrupt;

          HAL_FUNCTIONS *HalFunc; /* GSG 11/20 changed name to match cppi */
          bit32  Inst;
          DEVICE_STATE State;
          bit32 TxTeardownPending[MAX_CHAN];
          bit32 RxTeardownPending[MAX_CHAN];
          bit32 ChIsSetup[MAX_CHAN][2];
          bit32 dev_base;
          cppi_txcntl_s TxCtlBlk[MAX_CHAN][MAX_QUEUE];
          cppi_rxcntl_s RxCtlBlk[MAX_CHAN];
          CHANNEL_INFO ChData[MAX_CHAN];
          bit32  offset;
          bit32 InRxInt[MAX_CHAN];
          bit32 NeedsCount;
          HAL_RECEIVEINFO *Needs[MAX_NEEDS];
          FRAGLIST fraglist[MAX_FRAG];

          unsigned char MacAddr[6];
          int debug;
          bit32u IntVec;
          char id[20];
          bit8u MacAdr[6];
          }halDevice_s;

typedef volatile struct hal_private
  {
  bit32 HNext;      /*< Hardware's pointer to next buffer descriptor     */
  bit32 BufPtr;     /*< Pointer to the data buffer                       */
  bit32 Off_BLen;   /*< Contains buffer offset and buffer length         */
  bit32 mode;       /*< SOP, EOP, Ownership, EOQ, Teardown Complete bits */
  void *DatPtr;
  void *Next;
  void *OsInfo;
  HAL_DEVICE *HalDev;
  unsigned int Ch;
  void *Eop;
  bit32 FragCount;
  }hal_rcb_s;

typedef struct
          {
          bit32u HNext;
          bit32u HBuf;
          bit32u OffLen;
          bit32u Status;
          bit32u HNext2;
          bit32u HBuf2;
          bit32u OffLen2;
          bit32u Status2;
          }dcb_s;

#define        VirtToPhys(a)                 (((int)a)&~0xe0000000)
#define        VirtToVirtNoCache(a)          ((void*)((VirtToPhys(a))|0xa0000000))
#define        VirtToVirtCache(a)            ((void*)((VirtToPhys(a))|0x80000000))

#define  PDSP_COMMAND               (*(volatile unsigned *)(HalDev->EswitchBase+0x2800)) /*CmdCode*/
#define  PDSP_PARAM0                (*(volatile unsigned *)(HalDev->EswitchBase+0x2804)) /*Port*/
#define  PDSP_PARAM1                (*(volatile unsigned *)(HalDev->EswitchBase+0x2808)) /*arg0*/
#define  PDSP_PARAM2                (*(volatile unsigned *)(HalDev->EswitchBase+0x280c)) /*arg1*/
#define  PDSP_PARAM3                (*(volatile unsigned *)(HalDev->EswitchBase+0x2810)) /*arg2*/
#define  PDSP_PARAM4                (*(volatile unsigned *)(HalDev->EswitchBase+0x2814)) /*arg3*/
#define  PDSP_PARAM5                (*(volatile unsigned *)(HalDev->EswitchBase+0x2818)) /*Pulse*/
#define  PDSP_STATUS                (*(volatile unsigned *)(HalDev->EswitchBase+0x281c)) /*Status*/

#define  QUEUE_PTR_SIZE         (4*4)             /*Queue 4 words of 4 bytes       */
#define  ESWITCH_DESCRIPTOR_SIZE    (4*4*2)  /*Eswitch Rx Descriptor size 4 bytes*4 words*2descriptors*/
#define  ESWITCH_PORTS          3
#define  ESWITCH_CHANNELS_PER_PORT  8

#define  OWNERSHIP          (1<<29)

#define  PDSP_PCKMEM_BASE       (HalDev->EswitchBase+0x10000)
#define  PDSP_PCKMEM_EOFFSET        (0x10000)
#define  PDSP_PCKMEM_SIZE       (0x8000)
#define  PDSP_PCKMEM_FAILURE        0x80000001

#define  PDSP_IMEM_BASE         (HalDev->EswitchBase+0x8000)
#define  PDSP_IMEM_SIZE         (0x1000)
#define  PDSP_IMEM_FAILURE      0x80000002

#define  PDSP_IMEM_CTL              (*(volatile unsigned *)(PDSP_IMEM_BASE))
#define  PDSP_LOAD_FAILURE      0x80000003
#define  MALLOC_FAILURE         0x80000004
#define  PDSP_INT_RAMTEST_FAILURE   0x80000005
#define  PDSP_EXT_RAMTEST_FAILURE   0x80000006


#define  PDSP_PORTALADR             (*(volatile unsigned *)(HalDev->EswitchBase+0x2894)) /*Status*/
#define  PDSP_PORTALDAT             (*(volatile unsigned *)(HalDev->EswitchBase+0x2898)) /*Status*/




#define MIPS_NO_CMD         0x00
/*       port control commands                                               */
#define MIPS_ENABLE_PORT        0x01
#define MIPS_DISABLE_PORT       0x02
#define MIPS_SET_DUPLEX         0x03
#define MIPS_SET_PRIMAP         0x04
#define MIPS_SET_RX_Q           0x05
#define MIPS_SET_TX_Q           0x06
#define MIPS_INIT_PORT          0x07
#define MIPS_SET_PVID           0x08
#define MIPS_SET_RX_DESCPOOL        0x09
#define MIPS_SET_CPOS_DESCPOOL      0x0A
/*       switch control commands                                             */
#define MIPS_STP_PORT_MASK      0x20
#define MIPS_SET_MODE           0x21
#define MIPS_SET_MAC_ADDR       0x22
#define MIPS_SET_OVERFLOW_Q     0x23
#define MIPS_GET_OVERFLOW_Q     0x24
#define MIPS_WRITE_CAM          0x25
#define MIPS_READ_CAM           0x26
#define MIPS_RESTART_CAM        0x27
#define MIPS_SET_CAM_SIZE       0x28
#define MIPS_SET_TENTH_COUNT        0x29
#define MIPS_SET_AGE_INTERVAL       0x2A
#define MIPS_SET_PHY_INTERVAL       0x2B
#define MIPS_SET_CPMAC_BUFLEN       0x2C
#define MIPS_SET_OVER_BUFLEN        0x2D
#define PDSPCMD_CAM_OP          0x2E
/*      debug and test commands                                                  */
#define MIPS_PAUSE_PDSP         0x80
#define MIPS_RAMTEST            0x81
#define MIPS_DEBUG          0x82
#define MIPS_DUMP_REGS          0x83

#define MIPS_PING_PDSP          0xFF


#define PDSP_SS_TXCHAN              7
#define PDSP_IP_TXCHAN              1
#define PDSP_HOST_RXCHAN            0

#define  PDSP_RXQUEUERAM        (*(volatile unsigned *)(HalDev->EswitchBase+0x2840))
#define  PDSP_TXQUEUERAM        (*(volatile unsigned *)(HalDev->EswitchBase+0x2844))
#define  PDSP_SCRATCHPADRAM         (*(volatile unsigned *)(HalDev->EswitchBase+0x2848))
#define  PDSP_HDMAINTMASK       (*(volatile unsigned *)(HalDev->EswitchBase+0x284c))

#define  HDMA_TXENDIAN          (*(volatile unsigned *)(HalDev->HdmaBase+0x40))
#define  HDMA_RXENDIAN          (*(volatile unsigned *)(HalDev->HdmaBase+0x44))
#define  HDMA_TX_INTMASK_SET(base)  (*(volatile unsigned *)(base+0x178))
#define  HDMA_RX_INTMASK_SET(base)  (*(volatile unsigned *)(base+0x198))
#define  HDMA_EOI(base)             (*(volatile unsigned *)(base+0x184))

#define  HDMA_IN_VECTOR(base)       (*(volatile unsigned *)(base+0x180))


#define  ESWITCH_TICS_PER_SEC       10

/* Debug Stuff */

#define DBG(level)  (HalDev->debug & (1<<(level)))
#define dbgPrintf HalDev->OsFunc->Printf
#define osfuncSioFlush()  HalDev->OsFunc->Control(HalDev->OsDev,"SioFlush",0,0)

#include "cpswhalecerrors.h"

/*
ERROR REPORTING

HAL Module Codes.  Each HAL module reporting an error code
should OR the error code with the respective Module error code
from the list below.
*/
#define EC_HDMA                                EC_HAL|EC_DEV_HDMA
#define EC_AAL5                                EC_HAL|EC_DEV_AAL5
#define EC_AAL2                                EC_HAL|EC_DEV_AAL2
#define EC_CPSAR                               EC_HAL|EC_DEV_CPSAR
#define EC_CPMAC                               EC_HAL|EC_DEV_CPMAC
#define EC_VDMA                                EC_HAL|EC_DEV_VDMA
#define EC_VLYNQ                               EC_HAL|EC_DEV_VLYNQ
#define EC_ESWITCH                             EC_HAL|EC_DEV_ESWITCH
#define EC_CPPI                                EC_HAL|EC_DEV_CPPI

/*
HAL Function Codes.  Each HAL module reporting an error code
should OR the error code with one of the function codes from
the list below.
*/
#define EC_FUNC_HAL_INIT                       EC_FUNC(1)
#define EC_FUNC_CHSETUP                        EC_FUNC(2)
#define EC_FUNC_CHTEARDOWN                     EC_FUNC(3)
#define EC_FUNC_RXRETURN                       EC_FUNC(4)
#define EC_FUNC_SEND                           EC_FUNC(5)
#define EC_FUNC_RXINT                          EC_FUNC(6)
#define EC_FUNC_TXINT                          EC_FUNC(7)
#define EC_FUNC_AAL2_VDMA                      EC_FUNC(8)
#define EC_FUNC_OPTIONS                        EC_FUNC(9)
#define EC_FUNC_PROBE                          EC_FUNC(10)
#define EC_FUNC_OPEN                           EC_FUNC(11)
#define EC_FUNC_CONTROL                        EC_FUNC(12)
#define EC_FUNC_DEVICE_INT                     EC_FUNC(13)
#define EC_FUNC_STATUS                         EC_FUNC(14)
#define EC_FUNC_TICK                           EC_FUNC(15)
#define EC_FUNC_CLOSE                          EC_FUNC(16)
#define EC_FUNC_SHUTDOWN                       EC_FUNC(17)

/*
HAL Error Codes.  The list below defines every type of error
used in all HAL modules. DO NOT CHANGE THESE VALUES!  Add new
values in integer order to the bottom of the list.
*/
#define EC_VAL_PDSP_LOAD_FAIL                 EC_ERR(0x01)|EC_CRITICAL
#define EC_VAL_FIRMWARE_TOO_LARGE             EC_ERR(0x02)|EC_CRITICAL
#define EC_VAL_DEVICE_NOT_FOUND               EC_ERR(0x03)|EC_CRITICAL
#define EC_VAL_BASE_ADDR_NOT_FOUND            EC_ERR(0x04)|EC_CRITICAL
#define EC_VAL_RESET_BIT_NOT_FOUND            EC_ERR(0x05)|EC_CRITICAL
#define EC_VAL_CH_INFO_NOT_FOUND              EC_ERR(0x06)
#define EC_VAL_RX_STATE_RAM_NOT_CLEARED       EC_ERR(0x07)|EC_CRITICAL
#define EC_VAL_TX_STATE_RAM_NOT_CLEARED       EC_ERR(0x08)|EC_CRITICAL
#define EC_VAL_MALLOC_DEV_FAILED              EC_ERR(0x09)
#define EC_VAL_OS_VERSION_NOT_SUPPORTED       EC_ERR(0x0A)|EC_CRITICAL
#define EC_VAL_CPSAR_VERSION_NOT_SUPPORTED    EC_ERR(0x0B)|EC_CRITICAL
#define EC_VAL_NULL_CPSAR_DEV                 EC_ERR(0x0C)|EC_CRITICAL

#define EC_VAL_LUT_NOT_READY                  EC_ERR(0x0D)
#define EC_VAL_INVALID_CH                     EC_ERR(0x0E)
#define EC_VAL_NULL_CH_STRUCT                 EC_ERR(0x0F)
#define EC_VAL_RX_TEARDOWN_ALREADY_PEND       EC_ERR(0x10)
#define EC_VAL_TX_TEARDOWN_ALREADY_PEND       EC_ERR(0x11)
#define EC_VAL_RX_CH_ALREADY_TORNDOWN         EC_ERR(0x12)
#define EC_VAL_TX_CH_ALREADY_TORNDOWN         EC_ERR(0x13)
#define EC_VAL_TX_TEARDOWN_TIMEOUT            EC_ERR(0x14)
#define EC_VAL_RX_TEARDOWN_TIMEOUT            EC_ERR(0x15)
#define EC_VAL_CH_ALREADY_TORNDOWN            EC_ERR(0x16)
#define EC_VAL_VC_SETUP_NOT_READY             EC_ERR(0x17)
#define EC_VAL_VC_TEARDOWN_NOT_READY          EC_ERR(0x18)
#define EC_VAL_INVALID_VC                     EC_ERR(0x19)
#define EC_VAL_INVALID_LC                     EC_ERR(0x20)
#define EC_VAL_INVALID_VDMA_CH                EC_ERR(0x21)
#define EC_VAL_INVALID_CID                    EC_ERR(0x22)
#define EC_VAL_INVALID_UUI                    EC_ERR(0x23)
#define EC_VAL_INVALID_UUI_DISCARD            EC_ERR(0x24)
#define EC_VAL_CH_ALREADY_OPEN                EC_ERR(0x25)

#define EC_VAL_RCB_MALLOC_FAILED              EC_ERR(0x26)
#define EC_VAL_RX_BUFFER_MALLOC_FAILED        EC_ERR(0x27)
#define EC_VAL_OUT_OF_TCBS                    EC_ERR(0x28)
#define EC_VAL_NO_TCBS                        EC_ERR(0x29)
#define EC_VAL_NULL_RCB                       EC_ERR(0x30)|EC_CRITICAL
#define EC_VAL_SOP_ERROR                      EC_ERR(0x31)|EC_CRITICAL
#define EC_VAL_EOP_ERROR                      EC_ERR(0x32)|EC_CRITICAL
#define EC_VAL_NULL_TCB                       EC_ERR(0x33)|EC_CRITICAL
#define EC_VAL_CORRUPT_RCB_CHAIN              EC_ERR(0x34)|EC_CRITICAL
#define EC_VAL_TCB_MALLOC_FAILED              EC_ERR(0x35)

#define EC_VAL_DISABLE_POLLING_FAILED         EC_ERR(0x36)
#define EC_VAL_KEY_NOT_FOUND                  EC_ERR(0x37)
#define EC_VAL_MALLOC_FAILED                  EC_ERR(0x38)
#define EC_VAL_RESET_BASE_NOT_FOUND           EC_ERR(0x39)|EC_CRITICAL
#define EC_VAL_INVALID_STATE                  EC_ERR(0x40)
#define EC_VAL_NO_TXH_WORK_TO_DO              EC_ERR(0x41)
#define EC_VAL_NO_TXL_WORK_TO_DO              EC_ERR(0x42)
#define EC_VAL_NO_RX_WORK_TO_DO               EC_ERR(0x43)
#define EC_VAL_NOT_LINKED                     EC_ERR(0x44)
#define EC_VAL_INTERRUPT_NOT_FOUND            EC_ERR(0x45)
#define EC_VAL_OFFSET_NOT_FOUND               EC_ERR(0x46)
#define EC_VAL_MODULE_ALREADY_CLOSED          EC_ERR(0x47)
#define EC_VAL_MODULE_ALREADY_SHUTDOWN        EC_ERR(0x48)
#define EC_VAL_ACTION_NOT_FOUND               EC_ERR(0x49)
#define EC_VAL_RX_CH_ALREADY_SETUP            EC_ERR(0x50)
#define EC_VAL_TX_CH_ALREADY_SETUP            EC_ERR(0x51)
#define EC_VAL_RX_CH_ALREADY_OPEN             EC_ERR(0x52)
#define EC_VAL_TX_CH_ALREADY_OPEN             EC_ERR(0x53)
#define EC_VAL_CH_ALREADY_SETUP               EC_ERR(0x54)
#define EC_VAL_RCB_NEEDS_BUFFER               EC_ERR(0x55)
#define EC_VAL_RCB_DROPPED                    EC_ERR(0x56)

/* Functions */

#ifdef __GNUCx__
#define osfuncDataCacheHitWritebackAndInvalidate(ptr, Size)  asm(" cache  21, (%0)" : : "r" (ptr))
#define osfuncDataCacheHitInvalidate(ptr, Size) asm(" cache  17, (%0)" : : "r" (ptr))
#else
#define osfuncDataCacheHitInvalidate(ptr, Size)   HalDev->OsFunc->DataCacheHitInvalidate(ptr, Size)
#define osfuncDataCacheHitWritebackAndInvalidate(ptr, Size)    HalDev->OsFunc->DataCacheHitWriteback(ptr, Size)
#endif

#define osfuncSleep(Ticks)  HalDev->OsFunc->Control(HalDev->OsDev,pszSleep,pszNULL,Ticks)

/* Things that should not be in the halprivate!!!                            */

static const char pszSleep[]             = "Sleep";
static const char pszNULL[]              = "";



int cpswHalEswitchTestPdspRam(HAL_DEVICE *HalDev,char *name,bit32u base,bit32u size);
int cpswHalEswitchPdspLoad(HAL_DEVICE *HalDev);
int cpswHalEswitchPdspCmdRamTest(HAL_DEVICE *HalDev,bit32u base, bit32u size);
int cpswHalEswitchPdspCmdSetTenthCount(HAL_DEVICE *HalDev,bit32u ClocksPerTic);
int cpswHalEswitchPdspCmdSetAgeInterval(HAL_DEVICE *HalDev,bit32u TicsPerInterval);
int cpswHalEswitchPdspCmdSetPhyInterval(HAL_DEVICE *HalDev,bit32u TicsPerInterval);
int cpswHalEswitchPdspCmdRestartCam(HAL_DEVICE *HalDev);
int cpswHalEswitchPdspCmdSetCamSize(HAL_DEVICE *HalDev,bit32u size);
int cpswHalEswitchPdspCmdSetMode(HAL_DEVICE *HalDev,bit32u mode);  /*Export */
int cpswHalEswitchPdspCmdStpPortMask(HAL_DEVICE *HalDev,bit32u mask);  /*Export*/
int cpswHalEswitchPdspCmdSetRxQueue(HAL_DEVICE *HalDev,bit32u ChanPort, bit32u head,bit32 tail,bit32u count);
int cpswHalEswitchPdspCmdSetDescPool(HAL_DEVICE *HalDev,bit32u RxPort0Desc, bit32u RxPort1Desc,bit32 RxPort2Desc,bit32u RxPort3Desc);
int cpswHalEswitchPDSPCommand(HAL_DEVICE *HalDev,bit32u command,bit32u p1, bit32u p2,bit32 p3,bit32u p4);
int cpswHalEswitchPdspCmdSetTxQueue(HAL_DEVICE *HalDev,bit32u ChanPort, bit32u head,bit32 tail,bit32u count);
int cpswHalEswitchPdspCmdSetBufLen(HAL_DEVICE *HalDev,bit32u mask);
int cpswHalEswitchPdspCmdSetPriorityMapping(HAL_DEVICE *HalDev,bit32u Port, bit32u InputPriority,bit32 Mapping); /*Export*/
int cpswHalEswitchPdspCmdInitPort(HAL_DEVICE *HalDev,bit32u port);
int cpswHalEswitchPdspCmdSetDuplex(HAL_DEVICE *HalDev,bit32u port, bit32u duplex);
int cpswHalEswitchPdspCmdSetPortVlanId(HAL_DEVICE *HalDev,bit32u port, bit32u vlanid);  /*Export*/
int cpswHalEswitchPdspCmdEnablePort(HAL_DEVICE *HalDev,bit32u port);  /*Export*/
int cpswHalEswitchPdspCmdDisablePort(HAL_DEVICE *HalDev,bit32u port);  /*Export*/
int cpswHalEswitchPdspCmdCamOp(HAL_DEVICE *HalDev,bit32u Mode,bit32u DatLo,bit32 DatHi,bit32u *Status);
int cpswHalEswitchPdspCmdWriteCam(HAL_DEVICE *HalDev,bit32u Adr, bit32u DatLo,bit32 DatHi,bit32u *Status);
int cpswHalEswitchPdspCmdReadCam(HAL_DEVICE *HalDev,bit32u Adr, bit32u *DatLo,bit32 *DatHi,bit32u *Status);
int cpswHalEswitchInitHdmaPort(HAL_DEVICE *HalDev);
int cpswHalEswitchError(HAL_DEVICE *HalDev,char *str);
int  cpswHalEswitchOverFlowQueueInit(HAL_DEVICE *HalDev,int count, int size,int threshold,int topoffto);
int  cpswHalEswitchQueueInit(HAL_DEVICE *HalDev,int Port,int Channel,bit32u HeadPtr,bit32u BufPtr,int Count,int Size);
int  cpswHalEswitchPdspCmdWait(HAL_DEVICE *HalDev);
int  cpswHalEswitchPdspCmdSetOverflowQueue(HAL_DEVICE *HalDev,bit32u head, bit32u tail,bit32 count,bit32u overctl);
int  cpswHalEswitchPdspCmdSetOverflowBufLen(HAL_DEVICE *HalDev,bit32u size);
int cpswHalEswitchInitCposPool(HAL_DEVICE *HalDev,int count);

int  cpswHalEswitchChannelSetup(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn, OS_SETUP *OsSetup);
int  cpswHalEswitchChannelTeardown(HAL_DEVICE *HalDev, int Channel, int Mode);
int  cpswHalEswitchClose(HAL_DEVICE *HalDev, int Mode);
int  cpswHalEswitchControl(HAL_DEVICE *HalDev, const char *Key, int Action, void *Value);
int  cpswHalEswitchInit(HAL_DEVICE *HalDev);
int  cpswHalEswitchOpen(HAL_DEVICE *HalDev);
int  cpswHalEswitchPacketProcessEnd(HAL_DEVICE *HalDev);
int  cpswHalEswitchProbe(HAL_DEVICE *HalDev);
int  cpswHalEswitchRxReturn(HAL_RECEIVEINFO *HalReceiveInfo, int StripFlag);
int  cpswHalEswitchSend(HAL_DEVICE *HalDev,FRAGLIST *FragList,int FragCount,int PacketSize, OS_SENDINFO *OsSendInfo,int (*SendComplete)(OS_SENDINFO *),bit32u Mode);
int  cpswHalEswitchShutdown(HAL_DEVICE *HalDev);
int  cpswHalEswitchTick(HAL_DEVICE *HalDev);

int halIsr(HAL_DEVICE *HalDev, int *MorePackets);

int cpswHalEswitchChannelConfigApply(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn);
int cpswHalEswitchMacAddressSet(HAL_DEVICE *HalDev);
int cpswHalEswitchGetConfig(HAL_DEVICE *HalDev);
int cpswHalEswitchInitParams(HAL_DEVICE *HalDev);
int cpswHalEswitchCheckAllParams(HAL_DEVICE *HalDev);
int cpswHalEswitchInitTcb(HAL_DEVICE *HalDev, int Ch);
int cpswHalEswitchTxInt(HAL_DEVICE *HalDev, int Ch, int Queue, int *MoreWork);
int cpswHalEswitchRxInt(HAL_DEVICE *HalDev, int Ch, int *MoreWork);
int cpswHalEswitchInitRcb(HAL_DEVICE *HalDev, int Ch);

int  cpswHalEswitchDisablePort(HAL_DEVICE *HalDev,bit32u port);
int  cpswHalEswitchEnablePort(HAL_DEVICE *HalDev,bit32u port);
int  cpswHalEswitchEnableMode(HAL_DEVICE *HalDev,bit32u mode);
int  cpswHalEswitchDisableMode(HAL_DEVICE *HalDev,bit32u mode);
int  cpswHalEswitchCamDump(HAL_DEVICE *HalDev);
int  cpswHalEswitchCamAddAddress(HAL_DEVICE *HalDev,char *addr,bit32u VlanId,bit32u Member);
int  cpswHalEswitchCamAddVlan(HAL_DEVICE *HalDev,bit32u VlanId,bit32u MemberSet,bit32u FwdAllMulticast,bit32u FwdUnregMulticast,bit32u FwdUntagged);
int  cpswHalEswitchCamDelAddress(HAL_DEVICE *HalDev,char *addr,bit32u VlanId);
int  cpswHalEswitchCamDelVlan(HAL_DEVICE *HalDev,bit32u VlanId);
int  cpswHalEswitchCamFindAddress(HAL_DEVICE *HalDev,char *addr,bit32u VlanId,bit32u *member);
int  cpswHalEswitchCamFindVlan(HAL_DEVICE *HalDev,bit32u VlanId,bit32u *MemberSet,bit32u *FwdAllMulticast,bit32u *FwdUnregMulticast,bit32u *FwdUntagged);
int  cpswHalEswitchEnableVIDIngress(HAL_DEVICE *HalDev,bit32u Port);
int  cpswHalEswitchDisableVIDIngress(HAL_DEVICE *HalDev,bit32u Port);
int  cpswHalEswitchEnableDropUnTaggedIngress(HAL_DEVICE *HalDev,bit32u Port);
int  cpswHalEswitchDisableDropUnTaggedIngress(HAL_DEVICE *HalDev,bit32u Port);
int  cpswHalEswitchSetPriorityMapping(HAL_DEVICE *HalDev, bit32u Port, bit32u InputPriority, bit32u OutputPriority, bit32u OutputChannel);
int  cpswHalEswitchSetPortVlanId(HAL_DEVICE *HalDev, bit32u Port, bit32u VlanId);
int  cpswHalEswitchStpPortState(HAL_DEVICE *HalDev, bit32u Port, STP_STATE State);
int  cpswHalEswitchSetAgeInterval(HAL_DEVICE *HalDev,bit32u count);

int  cpswHalEswitchIsr(HAL_DEVICE *HalDev, int *MorePackets);

#define dbgSioFlush SioFlush

#ifdef __CPHAL_DEBUG
#define dbgprint(DebugFlag, format, args...)  \
  {                                           \
  if (HalDev->debug&(DebugFlag))              \
    {                                         \
    dbgPrintf(format, ## args);               \
    osfuncSioFlush();                         \
    }                                         \
  }
#else
#define dbgprint(DebugFlag, format, args...)  {}
#endif

#include "cpswhalutlsupport.h"


/* CPPI registers */
#define TRANSMIT_PORT_TEARDOWN_REG(base)      (*(volatile unsigned *)(base+0x008))
#define TX_DMA_STATE_HDP(base,ch,q)           (*(volatile unsigned *)(base+0x600+(ch*4)))
#define TX_DMA_STATE_CP(base,ch,q)            (*(volatile unsigned *)(base+0x640+(ch*4)))
/*#define RECEIVE_PORT_TEARDOWN_REG(base)       (*(volatile unsigned *)(base+0x2800))*/
#define RX_DMA_STATE_HDP(base,ch)             (*(volatile unsigned *)(base+0x620+(ch*4)))
#define RX_DMA_STATE_CP(base,ch)              (*(volatile unsigned *)(base+0x660+(ch*4)))
#define HDMA_FREE_BUFFER_COUNT(base,ch)       (*(volatile unsigned *)(base+0x140+(ch*4)))

/* the following defines are not CPPI specific, but still used by cppi.c */
#define MODULE_ERROR       EC_ESWITCH
#define HIGHEST_CHANNEL    7

#define CPPI_RX_CONTROL(base)                  (*(volatile unsigned *)(base+0x14))
#define CPPI_TX_CONTROL(base)                  (*(volatile unsigned *)(base+0x04))
#define CPPI_MAC_CONTROL(base)                 (*(volatile unsigned *)(base+0x160))

#define MII_EN (1<<5)
#define TX_EN (1<<0)
#define RX_EN (1<<0)

/* New features in 2.0 support package */

#define cpswHalCommonmemset cpswHalUtlmemset
#define haCLEAR hcClear
#define HAL_CONTROL_KEY const char
