/*------------------------------------------------------------------------------------------*\
 *
 *  $Id$
 *
 *  $Log$
 *
\*------------------------------------------------------------------------------------------*/
#ifndef _ohio_nand_h_
#define _ohio_nand_h_

#define OHIO_NAND_DELAY     1
#define OHIO_NAND_NO_DELAY  0

enum __nand_command {
		cmd_reset=0,               /*--- Reset ---*/
		cmd_read_status=1,         /*--- Status Read ---*/
		cmd_read_id=2,             /*--- ID Read ---*/
		cmd_auto_block_erase=3,    /*--- Auto block erase ---*/
		cmd_auto_page_program=5,   /*--- Auto Page Program ---*/
        cmd_read=6,
		/*--- cmd_reserved = 0x5; ---*/            /*--- Reserved ---*/
		/*--- cmd_serial_data_out = 0x6; ---*/     /*--- Serial Data Output (=Read) ---*/
		/*--- cmd_serial_data_in = 0x7 ---*/       /*--- Serial Data Input (= Write) ---*/
};

struct __nand {
	unsigned char Buffer[2112];                 /*--- OFFSET: 0x0000 ---*/
	unsigned char reserved[0x1FF8 - 0x1844];    /*--- OFFSET: 0x0844 ---*/
	union __nand_control {                      /*--- OFFSET: 0x0FF8 ---*/
		struct _nand_control {
			unsigned int page_addr : 24;
			enum __nand_command cmd : 3;
			unsigned int reserved1 : 2;
			unsigned int write_protect : 1;
            unsigned int chip_select : 2;
        } Bits;
        unsigned int Register;
    } nand_control;
	union __nand_status {                       /*--- OFFSET 0x0FFC ---*/
		struct _nand_status {
            unsigned int failed : 1;
            unsigned int not_used25 : 4;
            unsigned int ready : 1;
            unsigned int nbusy : 1;
            unsigned int wp : 1;
            unsigned int irq : 1;
        } Bits;
        unsigned int Register;
    } nand_status;
};

typedef struct __nand        t_ohio_nand;
typedef union __nand_control t_ohio_nand_control;
typedef union __nand_status  t_ohio_nand_status;

#endif /*--- #ifndef _ohio_nand_h_ ---*/
