/******************************************************************************
     Copyright (c) 2004, Infineon Technologies.  All rights reserved.
     Copyright (C) 2006 AVM GmbH <fritzbox_info@avm.de>

                               No Warranty
   Because the program is licensed free of charge, there is no warranty for
   the program, to the extent permitted by applicable law.  Except when
   otherwise stated in writing the copyright holders and/or other parties
   provide the program "as is" without warranty of any kind, either
   expressed or implied, including, but not limited to, the implied
   warranties of merchantability and fitness for a particular purpose. The
   entire risk as to the quality and performance of the program is with
   you.  should the program prove defective, you assume the cost of all
   necessary servicing, repair or correction.

   In no event unless required by applicable law or agreed to in writing
   will any copyright holder, or any other party who may modify and/or
   redistribute the program as permitted above, be liable to you for
   damages, including any general, special, incidental or consequential
   damages arising out of the use or inability to use the program
   (including but not limited to loss of data or data being rendered
   inaccurate or losses sustained by you or third parties or a failure of
   the program to operate with any other programs), even if such holder or
   other party has been advised of the possibility of such damages.
 *****************************************************************************/
#ifndef _ADM6996_H_
#define _ADM6996_H_

/* command codes */
#define ADM_SW_SMI_READ     0x02
#define ADM_SW_SMI_WRITE    0x01
#define ADM_SW_SMI_START    0x01

#define ADM_SW_EEPROM_WRITE     0x01
#define ADM_SW_EEPROM_WRITE_ENABLE  0x03
#define ADM_SW_EEPROM_WRITE_DISABLE 0x00
#define EEPROM_TYPE     8   /* for 93C66 */

/* bit masks */
#define ADM_SW_BIT_MASK_1   0x00000001
#define ADM_SW_BIT_MASK_2   0x00000002
#define ADM_SW_BIT_MASK_4   0x00000008
#define ADM_SW_BIT_MASK_10  0x00000200
#define ADM_SW_BIT_MASK_16  0x00008000
#define ADM_SW_BIT_MASK_32  0x80000000

/* delay timers */
#define ADM_SW_MDC_DOWN_DELAY   5
#define ADM_SW_MDC_UP_DELAY     5
#define ADM_SW_CS_DELAY         5

/* MDIO modes */
#define ADM_SW_MDIO_OUTPUT  0
#define ADM_SW_MDIO_INPUT   1

/*  ADMTEK 6996LC 16 BIT Mode Register Definitions                          */
#define REG_ADM_LC_SIGNATURE    0x00
#define REG_ADM_LC_PORT0_CONF   0x1
#define REG_ADM_LC_PORT1_CONF   0x3
#define REG_ADM_LC_PORT2_CONF   0x5
#define REG_ADM_LC_PORT3_CONF   0x7
#define REG_ADM_LC_PORT4_CONF   0x8
#define REG_ADM_LC_PORT5_CONF   0x9
  #define ADM_CONF_FLOW_CONTROL            (1 <<  0)
  #define ADM_CONF_AUTO_NEGOTIATION        (1 <<  1)
  #define ADM_CONF_SPEED_100               (1 <<  2)
  #define ADM_CONF_DUPLEX_FULL             (1 <<  3)
  #define ADM_CONF_OUTPUT_PKT_TAG          (1 <<  4)
  #define ADM_CONF_PORT_DISABLE            (1 <<  5)
  #define ADM_CONF_PORT_BASE_PRIO_ENABLE   (1 <<  6)
  #define ADM_CONF_PORT_BASE_PRIO          (3 <<  7)
  #define ADM_CONF_PORT_VLAN_ID            (15 << 10)
  #define ADM_CONF_SELECT_FX               (1 << 14)
  #define ADM_CONF_AUTO_MDIX               (1 << 15)
#define REG_ADM_LC_VLAN_MODE    0x11
#define REG_ADM_LC_MAC_LOCK     0x12
#define REG_ADM_LC_VLAN0_CONF   0x13
#define REG_ADM_LC_PORT0_PVID   0x28
#define REG_ADM_LC_PORT1_PVID   0x29
#define REG_ADM_LC_PORT2_PVID   0x2a
#define REG_ADM_LC_PORT34_PVID  0x2b
#define REG_ADM_LC_PORT5_PVID   0x2c
#define REG_ADM_LC_PHY_RESET    0x2f
#define REG_ADM_LC_MISC_CONF    0x30
#define REG_ADM_LC_BNDWDH_CTL0  0x31
#define REG_ADM_LC_BNDWDH_CTL1  0x32
#define REG_ADM_LC_BNDWDH_CTL_ENA   0x33

#define REG_ADM_LC_VLAN_FILTER0_LOW  0x40
#define REG_ADM_LC_VLAN_FILTER0_HIGH 0x41

#define REG_ADM_LC_ID                         0xa0
#define REG_ADM_LC_STATUS0                    0xa2
  #define ADM_STATUS_LINKUP                (1 <<  0)
  #define ADM_STATUS_SPEED                 (1 <<  1)
  #define ADM_STATUS_DUPLEX                (1 <<  2)
  #define ADM_STATUS_FLOWCONTROL           (1 <<  3)
/* Shift bits for ports 0-4 */
  #define ADM_STATUS_PORT0_SHIFT           0
  #define ADM_STATUS_PORT1_SHIFT           8
  #define ADM_STATUS_PORT2_SHIFT           16
  #define ADM_STATUS_PORT3_SHIFT           24
  #define ADM_STATUS_PORT4_SHIFT           28

  #define ADM_STATUS0_PORT0_LINKUP         (ADM_STATUS_LINKUP      << ADM_STATUS_PORT0_SHIFT)
  #define ADM_STATUS0_PORT0_SPEED          (ADM_STATUS_SPEED       << ADM_STATUS_PORT0_SHIFT)
  #define ADM_STATUS0_PORT0_DUPLEX         (ADM_STATUS_DUPLEX      << ADM_STATUS_PORT0_SHIFT)
  #define ADM_STATUS0_PORT0_FLOWCONTROL    (ADM_STATUS_FLOWCONTROL << ADM_STATUS_PORT0_SHIFT)
  #define ADM_STATUS0_PORT1_LINKUP         (ADM_STATUS_LINKUP      << ADM_STATUS_PORT1_SHIFT)
  #define ADM_STATUS0_PORT1_SPEED          (ADM_STATUS_SPEED       << ADM_STATUS_PORT1_SHIFT)
  #define ADM_STATUS0_PORT1_DUPLEX         (ADM_STATUS_DUPLEX      << ADM_STATUS_PORT1_SHIFT)
  #define ADM_STATUS0_PORT1_FLOWCONTROL    (ADM_STATUS_FLOWCONTROL << ADM_STATUS_PORT1_SHIFT)
  #define ADM_STATUS0_PORT2_LINKUP         (ADM_STATUS_LINKUP      << ADM_STATUS_PORT2_SHIFT)
  #define ADM_STATUS0_PORT2_SPEED          (ADM_STATUS_SPEED       << ADM_STATUS_PORT2_SHIFT)
  #define ADM_STATUS0_PORT2_DUPLEX         (ADM_STATUS_DUPLEX      << ADM_STATUS_PORT2_SHIFT)
  #define ADM_STATUS0_PORT2_FLOWCONTROL    (ADM_STATUS_FLOWCONTROL << ADM_STATUS_PORT2_SHIFT)
  #define ADM_STATUS0_PORT3_LINKUP         (ADM_STATUS_LINKUP      << ADM_STATUS_PORT3_SHIFT)
  #define ADM_STATUS0_PORT3_SPEED          (ADM_STATUS_SPEED       << ADM_STATUS_PORT3_SHIFT)
  #define ADM_STATUS0_PORT3_DUPLEX         (ADM_STATUS_DUPLEX      << ADM_STATUS_PORT3_SHIFT)
  #define ADM_STATUS0_PORT3_FLOWCONTROL    (ADM_STATUS_FLOWCONTROL << ADM_STATUS_PORT3_SHIFT)
  #define ADM_STATUS0_PORT4_LINKUP         (ADM_STATUS_LINKUP      << ADM_STATUS_PORT4_SHIFT)
  #define ADM_STATUS0_PORT4_SPEED          (ADM_STATUS_SPEED       << ADM_STATUS_PORT4_SHIFT)
  #define ADM_STATUS0_PORT4_DUPLEX         (ADM_STATUS_DUPLEX      << ADM_STATUS_PORT4_SHIFT)
  #define ADM_STATUS0_PORT4_FLOWCONTROL    (ADM_STATUS_FLOWCONTROL << ADM_STATUS_PORT4_SHIFT)

#define REG_ADM_LC_STATUS2                    0xa4
  #define ADM_STATUS2_PORT5_SHIFT           0

  #define ADM_STATUS_PORT5_LINKUP          (ADM_STATUS_LINKUP      << ADM_STATUS2_PORT5_SHIFT)
  #define ADM_STATUS_PORT5_SPEED           (ADM_STATUS_SPEED       << ADM_STATUS2_PORT5_SHIFT)
  #define ADM_STATUS_PORT5_DUPLEX          (ADM_STATUS_DUPLEX      << ADM_STATUS2_PORT5_SHIFT)
  #define ADM_STATUS_PORT5_FLOWCONTROL     (ADM_STATUS_FLOWCONTROL << ADM_STATUS2_PORT5_SHIFT)

#define REG_ADM_LC_RXPKTCNT0                  0xa8
#define REG_ADM_LC_RXPKTCNT1                  0xac
#define REG_ADM_LC_RXPKTCNT2                  0xb0
#define REG_ADM_LC_RXPKTCNT3                  0xb4
#define REG_ADM_LC_RXPKTCNT4                  0xb6
#define REG_ADM_LC_RXPKTCNT5                  0xb8
#define REG_ADM_LC_RXPKTBYTECNT0              0xba
#define REG_ADM_LC_RXPKTBYTECNT1              0xbe
#define REG_ADM_LC_RXPKTBYTECNT2              0xc2
#define REG_ADM_LC_RXPKTBYTECNT3              0xc6
#define REG_ADM_LC_RXPKTBYTECNT4              0xc8
#define REG_ADM_LC_RXPKTBYTECNT5              0xca
#define REG_ADM_LC_TXPKTCNT0                  0xcc
#define REG_ADM_LC_TXPKTCNT1                  0xd0
#define REG_ADM_LC_TXPKTCNT2                  0xd4
#define REG_ADM_LC_TXPKTCNT3                  0xd8
#define REG_ADM_LC_TXPKTCNT4                  0xda
#define REG_ADM_LC_TXPKTCNT5                  0xdc
#define REG_ADM_LC_TXPKTBYTECNT0              0xde
#define REG_ADM_LC_TXPKTBYTECNT1              0xe2
#define REG_ADM_LC_TXPKTBYTECNT2              0xe6
#define REG_ADM_LC_TXPKTBYTECNT3              0xea
#define REG_ADM_LC_TXPKTBYTECNT4              0xec
#define REG_ADM_LC_TXPKTBYTECNT5              0xee
#define REG_ADM_LC_COLLISIONCNT0              0xf0
#define REG_ADM_LC_COLLISIONCNT1              0xf4
#define REG_ADM_LC_COLLISIONCNT2              0xf8
#define REG_ADM_LC_COLLISIONCNT3              0xfc
#define REG_ADM_LC_COLLISIONCNT4              0xfe
#define REG_ADM_LC_COLLISIONCNT5              0x100
#define REG_ADM_LC_ERRCNT0                    0x102
#define REG_ADM_LC_ERRCNT1                    0x106
#define REG_ADM_LC_ERRCNT2                    0x10a
#define REG_ADM_LC_ERRCNT3                    0x10e
#define REG_ADM_LC_ERRCNT4                    0x110
#define REG_ADM_LC_ERRCNT5                    0x112

#define REG_ADM_LC_OVERFLOWFLAG0              0x114
  #define ADM_OVERFLOW_PKTCNT_PORT0        (1 <<  0)
  #define ADM_OVERFLOW_PKTCNT_PORT1        (1 <<  2)
  #define ADM_OVERFLOW_PKTCNT_PORT2        (1 <<  4)
  #define ADM_OVERFLOW_PKTCNT_PORT3        (1 <<  6)
  #define ADM_OVERFLOW_PKTCNT_PORT4        (1 <<  7)
  #define ADM_OVERFLOW_PKTCNT_PORT5        (1 <<  8)
  #define ADM_OVERFLOW_PKTBYTECNT_PORT0    (1 <<  9)
  #define ADM_OVERFLOW_PKTBYTECNT_PORT1    (1 << 11)
  #define ADM_OVERFLOW_PKTBYTECNT_PORT2    (1 << 13)
  #define ADM_OVERFLOW_PKTBYTECNT_PORT3    (1 << 15)
  #define ADM_OVERFLOW_PKTBYTECNT_PORT4    (1 << 16)
  #define ADM_OVERFLOW_PKTBYTECNT_PORT5    (1 << 17)

#define REG_ADM_LC_OVERFLOWFLAG2              0x116
#define REG_ADM_LC_OVERFLOWFLAG4              0x118
  #define ADM_OVERFLOW_COLLCNT_PORT0       (1 <<  0)
  #define ADM_OVERFLOW_COLLCNT_PORT1       (1 <<  2)
  #define ADM_OVERFLOW_COLLCNT_PORT2       (1 <<  4)
  #define ADM_OVERFLOW_COLLCNT_PORT3       (1 <<  6)
  #define ADM_OVERFLOW_COLLCNT_PORT4       (1 <<  7)
  #define ADM_OVERFLOW_COLLCNT_PORT5       (1 <<  8)
  #define ADM_OVERFLOW_ERRCNT_PORT0        (1 <<  9)
  #define ADM_OVERFLOW_ERRCNT_PORT1        (1 << 11)
  #define ADM_OVERFLOW_ERRCNT_PORT2        (1 << 13)
  #define ADM_OVERFLOW_ERRCNT_PORT3        (1 << 15)
  #define ADM_OVERFLOW_ERRCNT_PORT4        (1 << 16)
  #define ADM_OVERFLOW_ERRCNT_PORT5        (1 << 17)


/* port modes */
#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */
#define ADM_SW_PORT_AN      0x2 /* auto negotiation */
#define ADM_SW_PORT_100M    0x4 /* 100M */
#define ADM_SW_PORT_FULL    0x8 /* full duplex */
#define ADM_SW_PORT_TAG     0x10    /* output tag on */
#define ADM_SW_PORT_DISABLE 0x20    /* disable port */
#define ADM_SW_PORT_TOS     0x40    /* TOS first */
#define ADM_SW_PORT_PPRI    0x80    /* port based priority first */
#define ADM_SW_PORT_MDIX    0x8000  /* auto MDIX on */
#define ADM_SW_PORT_PVID_SHIFT  10
#define ADM_SW_PORT_PVID_BITS   4

/* VLAN */
#define ADM_SW_VLAN_PORT0   (1 << 0)
#define ADM_SW_VLAN_PORT1   (1 << 2)
#define ADM_SW_VLAN_PORT2   (1 << 4)
#define ADM_SW_VLAN_PORT3   (1 << 6)
#define ADM_SW_VLAN_PORT4   (1 << 7)
#define ADM_SW_VLAN_PORT5   (1 << 8)

#endif
